• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A multilayer wiring substrate has a passive circuit element disposed on an insulating base substrate, and an insulating layer is disposed on the insulating base substrate with the passive circuit element interposed therebetween. The insulating layer is formed to have via holes for exposing specific portions of the passive circuit element, and a terminal electrodes are disposed in the via holes. Accordingly, the entire area of the multilayer wiring substrate can be reduced, and cracks caused by residual stress produced by a firing step can be prevented.
    公开号:US20010003053A1
    申请号:US09/772,873
    申请日:2001-01-31
    公开日:2001-06-07
    发明作者:Takashi Nagasaka
    申请人:Denso Corp；
    IPC主号:H05K1-167
    专利说明:
    [0001] This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 9224281, filed on Aug. 5, 1997, the contents of which are incorporated herein by reference. [0001] BACKGROUND OF THE INVENTION
    [0002] 1. Field of the Invention [0002]
    [0003] This invention relates to a multilayer wiring substrate which is manufactured through a firing process and holds therein passive circuit elements such as a resistive element and an inductor element, and to a method of manufacturing the same. [0003]
    [0004] 2. Description of the Related Art [0004]
    [0005] When a thick-film resistive element is formed within multilayer wiring substrate for a hybrid integrated circuit, conventionally, as shown in FIG. 12, a plurality of conductive patterns [0005] 2 including a pair of resistive element terminal electrodes 2 a are formed on an insulating substrate 1 by printing and firing steps using conductive paste. Then, a thick-film resistive element 3 is formed across the pair of the terminal electrodes 2 a by printing and firing steps using resistive paste. The thick-film resistive element 3 and the conductive patterns 2 are covered with a protective overcoat glass (not shown).
    [0006] However, in the construction described above, the terminal electrodes [0006] 2 a and the thick-film resistive element 3 are arranged in a two-dimensional state, so that a region indicated with slant lines in FIG. 12 becomes a dead space for the thick-film resistive element 3. As a result, the area necessary for arranging the thick-film resistive element 3 becomes large, resulting in increase in entire area of the substrate. To solve this problem, recently, a substrate technique for forming a multilayer wiring substrate has been adopted. An example of this kind of substrate technique will be explained referring to FIGS. 14A to 14D.
    [0007] First, as shown in FIG. 14A, a plurality of conductive patterns [0007] 5 are formed on an insulating substrate 4 by printing and firing steps using conductive paste. The conductive patterns 5 includes a pair of terminal electrodes 5 a for a resistive element. The insulating substrate 4 is made of inorganic material. Next, as shown in FIG. 14B, a thick-film resistive element 6 is formed to be connected to the terminal electrodes 5 a on the insulating substrate 4 by printing and firing steps using resistive paste.
    [0008] After that, as shown in FIG. 14C, an insulating layer [0008] 7 made of for example glass material is formed on the insulating substrate 4 to have via holes 7 a for exposing the terminal electrodes 5 a and parts of the conductive patterns 5. As shown in FIG. 14D, then, terminal electrodes 8 filling the via holes 7 a and conductive patterns 9 disposed on the insulating layer 7 to be connected to the terminal electrodes 8 are formed by printing and firing steps using the conductive paste. Accordingly, a thick-film multilayer wiring substrate for a hybrid integrated circuit is completed. Incidentally, FIGS. 14A to 14D show the process for forming the thick-film wiring substrate having a two-layer structure in a stepwise manner; however when a thick-film multilayer wiring substrate having more than three layers is manufactured, after the printing and firing steps are carried out to form the terminal electrodes 8 and the conductive patterns 9, the steps shown in FIGS. 14A to 14D are repeatedly carried out.
    [0009] In the process described above, in the firing step for the insulating layer [0009] 7, a temperature is raised to approximately 850° C.-900° C. As opposed to this, a normal temperature range of the thick-film multilayer wiring substrate is comparatively low (for example −40° C.-150° C.). Accordingly, residual stress is produced due to a difference in thermal expansion coefficient between the thick-film resistive element 6 and the insulating layer 7.
    [0010] In the conventional structure, as shown in FIG. 13, the thick-film resistive element [0010] 6 swells up at overlapping portions with the terminal electrodes 5 a. Therefore, the residual stress is liable to concentrate on swelling portions A of the thick-film resistive element 6 to cause cracks. Likewise, the insulating layer 7 has portions B corresponding to the swelling portions A. The portions B of the insulating layer 7 have a thickness thinner than that of the peripheral portion thereof and slightly swell up along the swelling portions A of the thick-film resistive element 6. Accordingly, cracks may be generated at the portions B and may grow toward the thick-film resistive element 6. When the thick-film resistive element 6 has the cracks therein, its value of resistance deviates from the target value thereof, resulting in decrease in reliability. This kind of problem occurs in the so-called green sheet lamination method as well. SUMMARY OF THE INVENTION
    [0011] The present invention is made in view of the above problems. An object of the present invention is to reduce an entire area of a multilayer substrate. Another object of the present invention is to prevent cracks from being produced in a multilayer substrate due to residual stress generated by a firing step. Still another object of the present invention is to provide a method of manufacturing the multilayer substrate realizing the above objects. [0011]
    [0012] Briefly, in a multilayer substrate of the present invention, a passive circuit element is disposed above an insulating base substrate, and an insulating member is disposed on the insulating base substrate with the passive circuit member interposed therebetween. A via hole is formed through the insulating member to expose a part of the passive circuit element and a terminal electrode is disposed in the via hole. [0012]
    [0013] Accordingly, the terminal electrode is disposed on the passive circuit element without expanding from the passive circuit element in a direction parallel to the surface of the base substrate, so that the entire area of the multilayer substrate can be reduced. Because the passive circuit element has no overlapping portion partially overlapping with another layer, residual stress hardly concentrates on the passive circuit element, so that the passive circuit element is prevented from having cracks therein. [0013]
    [0014] The insulating base substrate can have a base substrate and an insulating layer disposed on the substrate. In this case, the passive circuit element is disposed on the insulating layer. The insulating base substrate can be composed of a plurality of green sheets laminated with one another. In this case, the insulating member is also composed of a green sheet. [0014]
    [0015] The multilayer substrate described above is manufactured by steps of: disposing a passive circuit element material at a specific portion on the insulating base substrate or on the insulating layer disposed on the base substrate; firing the passive circuit element material to form the passive circuit element; disposing an insulating material to cover the passive circuit element and to have a via hole for exposing the passive circuit element therefrom; firing the insulating material to form a thick-film insulating layer on the passive circuit element; filling the via hole with a conductive material; and firing the conductive material to form a terminal electrode in the via hole. [0015]
    [0016] The thick-film insulating layer can be formed by repeating the steps of disposing and firing the insulating material. The passive circuit element may be a resistive element. In this case, preferably, a step of trimming the resistive element is performed after the steps of disposing and firing the insulating material are carried out at least one time, respectively. Accordingly, a value of resistance of the resistive element can be precisely controlled. [0016] BRIEF DESCRIPTION OF THE DRAWINGS
    [0017] Other objects and features of the present invention will become more readily apparent from a better understanding of the preferred embodiments described below with reference to the following drawings; [0017]
    [0018] FIG. 1 is a cross-sectional view partially showing a multilayer wiring substrate in a first preferred embodiment; [0018]
    [0019] FIG. 2 is a plan view partially showing the multilayer wiring substrate of FIG. 1; [0019]
    [0020] FIGS. [0020] 3A-3F are cross-sectional views that illustrate a method of manufacturing the multilayer wiring substrate of FIG. 1 in a stepwise manner;
    [0021] FIG. 4 is a cross-sectional view partially showing a multilayer wiring substrate in a second preferred embodiment; [0021]
    [0022] FIG. 5 is a plan view partially showing the multilayer wiring substrate of FIG. 4; [0022]
    [0023] FIG. 6 is a cross-sectional view partially showing a multilayer wiring substrate in a third preferred embodiment; [0023]
    [0024] FIG. 7 is a cross-sectional view partially showing a multilayer wiring substrate in a fourth preferred embodiment; [0024]
    [0025] FIG. 8 is a circuit diaphragm of resistors in a modified embodiement of the first embodiment; [0025]
    [0026] FIG. 9 is a cross-sectional view partially showing a multilayer wiring substrate for realizing the circuit diaphragm of FIG. 8 therein; [0026]
    [0027] FIG. 10 is a circuit diaphragm of resistors in another modified embodiment of the first embodiment; [0027]
    [0028] FIG. 11 is a cross-sectional view partially showing a multilayer wiring substrate for realizing the circuit diaphragm of FIG. 10 therein; [0028]
    [0029] FIG. 12 is a plan view partially showing a part of a multilayer wiring substrate in a prior art; [0029]
    [0030] FIG. 13 is a cross-sectional view partially showing the multilayer wiring substrate in the prior art; and [0030]
    [0031] FIGS. [0031] 14A-14D are cross-sectional views that illustrate a method of maunufacturing the multilayer1 wiring substrate of FIG. 13 in a stepwise manner. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
    [0032] (First Embodiment) [0032]
    [0033] Referring to FIGS. 1, 2, a thick-film multilayer wiring substrate [0033] 10 in a first preferred embodiment has an insulating substrate 11 for serving as a base, which is made of inorganic material such as alumina, aluminum nitride (AlN), or silicon carbide (SiC). A thick-film resistive element (passive circuit element) 12 and a plurality of inside conductive patterns 13 are formed on the upper surface of the insulating substrate 11. The inside conductive patterns preferably include one of silver (Ag) and copper (Cu). When the inside conductive patterns 13 include Ag, the thick-film resistive element 12 preferably includes ruthenium oxide (RuO2). When the inside conductive patterns 13 include Cu, the thick-film resistive element 12 preferably includes at least one of lanthanum boride (LaB6) and tin oxide (SnO2).
    [0034] A thick-film insulating layer (insulating member) [0034] 14 is laminated with the insulating substrate 11 through the thick-film resistive element 12 and the inside conductive patterns 13. Accordingly, the thick-film resistive element 12 is disposed within the multilayer wiring substrate 10. The thick-film insulating layer 14 is made of inorganic material such as glass system material, ceramic system material, or glass-ceramic system material. A plurality of via-holes 15 are formed to penetrate the insulating layer 14 and to expose both end portions (corresponding to terminal portions) of the thick-film resistive element 12 and specific portions of the inside conductive patterns 13.
    [0035] Then, terminal electrodes [0035] 12 a, 13 a for the thick-film resistive element 12 and for the inside conductive patterns 13 are respectively formed in the via-holes 15 to electrically communicate with the thick-film resistive element 12 and the inside conductive patterns 13, respectively. Further, surface conductive patterns 17 are formed on the insulating layer 14. If necessary, the surface conductive patterns 17 may be plated with copper, nickel, or gold. Further, electrical components (not shown) such as IC chips and chip components are mounted on the thus constructed multilayer wiring substrate 10. The electrical components can be covered with a protective overcoat glass, if necessary.
    [0036] Next, a method of manufacturing the multilayer wiring substrate [0036] 10 will be explained with reference to FIGS. 3A to 3F. First, as shown in FIG. 3A, in an element formation step, resistive paste (thick-film paste material) for the thick-film resistive element 12 and conductive paste for the inside conductive patterns 13 are successively printed on the insulating substrate 11 and are baked. Accordingly, the thick-film resistive element 12 and the inside conductive patterns 13 are formed. In this embodiment, although the printed resistive paste and conductive paste are simultaneously baked to simplify the step, they may be separately baked in respective firing steps.
    [0037] Next, as shown in FIG. 3B, in an insulating layer formation step, insulating paste including for example glass is printed on the insulating substrate [0037] 11 to form a plurality of via holes 15 a for exposing the both end portions of the resistive element 12 and the specific portions of the inside conductive patterns 13. Then the printed insulating paste is baked. Accordingly, an insulating layer lower part 14 a of the insulating layer 14 is formed on the insulating substrate 11. Then, as shown in FIG. 13C, in a first electrode formation step, the via holes 15 a penetrating the insulating layer lower part 14 a is filled with the conductive paste by printing, and the conductive paste in the via holes 15 a is baked. Accordingly, terminal electrode lower parts 12 b, 13 b of the terminal electrodes 12 a, 13 a are respectively formed in the insulating layer lower part 14 a.
    [0038] After the first insulating layer formation step or after the first electrode formation step, a trimming step is carried out to adjust a value of resistance of the thick-film resistive element [0038] 12. FIG. 3D schematically show the trimming step which is carried out after the first insulating formation step as an example. In the trimming step, the value of resistance of the thick-film resistive element 12 is adjusted by laser trimming while being measured by a pair of probes contacting a pair of the terminal electrode lower parts 12 a, which are provided on the both end portions of the thick-film resistive element 12. At that time, a part of the insulating layer lower part 14 a is removed. As a technique for trimming the thick-film resistive element 12, a sand-blast trimming, a pulse trimming or the like may be utilized in stead of the laser trimming technique. When the pulse trimming technique is adopted, even in a state where the thick-film resistive element 12 is covered with another layer, the resistive element 12 can be trimmed so that the value of resistance of the resistive element 12 is controlled.
    [0039] After the trimming step is carried out, as shown in FIG. 3E, in a second insulating layer formation step, the insulating paste is printed on the insulating layer lower part [0039] 14 a to have a plurality of via holes 15 b at positions corresponding to the via holes 15 a, and then is baked. Accordingly, an insulating layer upper part 14 b having the via holes 15 b therein is formed on the insulating lower part 14 a. In the this embodiment, in this way, the insulating layer 14 is formed by the first and second insulating layer formation steps, i.e., by repeating the formation step twice. Because of this, the insulating paste can be printed without having babbles therein, so that insulating reliability of the insulating layer 14 is increased. Although the insulating layer 14 is formed by performing the formation step twice in this embodiment, it may be formed by performing the formation step more than twice in order to further improve the insulating reliability.
    [0040] Subsequently, as shown in FIG. 3F, in a second electrode formation step, the conductive paste is printed on the insulating layer upper part [0040] 14 b to fill the via holes 15 b and to form the surface conductive patterns 17 and then is baked. Accordingly, terminal electrode upper parts 12 c, 13 c, and the surface conductive patterns 17 are formed. Consequently, the thick-film multilayer wiring substrate 10 shown in FIG. 1 is completed.
    [0041] In this embodiment, the firing operation in each step described above is performed by the so-called air firing step. In accordance with that, the conductive paste includes noble metal system material such as silver (Ag), or Ag-platinum (Pt) system material, and the resistive paste includes ruthenium (Ru) system material. [0041]
    [0042] The terminal electrodes [0042] 12 a for the thick-film resistive element 12 are formed by filling the via holes 15 with the conductive paste and by firing the conductive paste in the via holes 15. Therefore, the terminal electrodes 12 a and the thick-film resistive element 12 are disposed in a three-dimensional state. As shown in FIG. 2, the terminal electrodes 12 a can be formed just above the thick-film resistive member 12 without expanding from the thick-film resistive element 12 in a direction parallel to the surface of the insulating film 14. As a result, the entire area of the multilayer wiring substrate 10 can be reduced as compared to that shown in FIG. 12.
    [0043] The thick-film resistive element [0043] 12 is directly formed on the insulating substrate 11 without any layers interposed therebetween. Therefore, the thick-film resistive element 12 does not swell up due to an overlapping portion with another layer as in the conventional structure shown in FIG. 13. Therefore, even when a residual stress is generated due to a difference in thermal expansion coefficient between the insulating layer 14 and the thick-film resistive element 12 after the firing steps of the first and second insulating layer formation steps, it is difficult for the residual stress to concentrate on a part of the thick-film resistive element 12. As a result, the thick-film resistive element 12 is prevented from having cracks therein.
    [0044] Also, in this embodiment, the trimming step for the thick-film resistive element [0044] 12 is carried out at a state where the insulating layer lower part 14 a and the terminal electrode lower parts 12 b are respectively formed in the first insulating layer formation step and in the first electrode formation step, i.e., in a state where the thickness of the insulating layer is relatively thin. Therefore, it is easy to perform the trimming step. Incidentally, the value of resistance of the resistive element 12 is easily increased during the firing step of the insulating layer 14 by invasion of components from the insulating layer 14 into the resistive element 12 or reaction between components of the resistive element 12 and the insulating layer 14. Therefore, in this embodiment, the trimming step for the resistive element 12 is performed after the insulating layer lower part 14 a is formed.
    [0045] That is, generally, in the case where the thick-film insulating layer [0045] 14 is formed by performing the formation step several times, the change in resistance of the thick-film resistive element 12 is largely effected by the formation step for forming the first layer directly contacting the thick-film resistive element 12, and is hardly effected by the subsequent formation steps for forming the upper layers than the first layer. Therefore, when the trimming step for the thick-film resistive element 12 is carried out after the insulating layer lower part 14 a is formed as in the first embodiment, the value of resistance of the thick-film resistive element 12 is prevented from largely deviating from its initial value after the trimming step. In addition, because the thickness of the insulating layer lower part 14 a is relatively thin as mentioned above, the trimming step is readily performed.
    [0046] In the first embodiment, the trimming step is performed after the terminal electrode lower parts [0046] 12 b are formed; however, it may be performed immediately after the insulating layer lower part 14 a is formed. In this case, the probes 16 directly contacts the both end portions of the thick-film resistive element 12 to measure the value of resistance.
    [0047] (Second Embodiment) [0047]
    [0048] FIGS. 4, 5 show a second preferred embodiment, and herebelow only points different from the first embodiment will be explained. The same parts as in the first embodiment are indicated with the same reference numerals. [0048]
    [0049] That is, in the second embodiment, a spiral thick-film resistive element [0049] 18 is formed on the insulating substrate 11 by printing and firing steps of resistive paste. In this case, the insulating layer 14 formed on the insulating substrate 11 through the thick-film resistive element 18 is formed with a pair of via holes 19 opening at the both end portions (corresponding to terminal portions) of the thick-film resistive element 18. Terminal electrodes 18 a for the thick-film resistive element 18 for filling in the via holes 19 and surface conductive patterns 20 are simultaneously formed in and on the insulating layer 14 by printing and firing steps using conductive paste.
    [0050] According to this embodiment, a surge withstand property of the thick-film resistive element [0050] 18 is improved. That is, generally, field intensity E applied to a resistor is expressed by formula; E=V/L, in which L represents a length of the resistor and V represents an applied voltage. Therefore, as in this embodiment, when the length of the thick-film resistive element 18 becomes long, the surge withstand property of the thick-film resistive element 18 becomes large. In addition, when a large value of resistance is required for the thick-film resistive element 18, an area necessary for arranging the thick-film resistive element 18 is relatively small. The other features and effects are the same as those in the first embodiment.
    [0051] (Third Embodiment) [0051]
    [0052] FIG. 6 shows a third preferred embodiment, and only points different from the first embodiment will be explained. That is, the third embodiment is most characterized in that two thick-film insulating layers [0052] 21, 22 are laminated on the insulating substrate 11 to form a thick-film multilayer wiring substrate 10 a. Specifically, referring to FIG. 6, a plurality of inside conductive patterns 23 are formed directly on the upper surface of the insulating substrate 11 by printing and firing steps using conductive paste. The thick-film resistive element may be directly formed on the upper surface of the insulating substrate 11. The thick-film insulating layer 21 made of inorganic material is then formed on the insulating substrate 11 with the inside conductive patterns 23 interposed therebetween by printing and firing steps.
    [0053] A plurality of via holes [0053] 24 are formed in the thick-film insulating layer 21 to expose specific portions of the inside conductive patterns 23, and the thick-film resistive element 12 is formed on the thick-film insulating layer 21 by printing and firing steps using resistive paste. Further, terminal electrodes 23 a are formed in the thick-film insulating layer 21 to fill the via holes 24, and at the same time inside conductive patterns 25 are formed on the thick-film insulating layer 21. The thick-film insulating layer 22 made of the same inorganic material as that of the thick-film insulating layer 21 is then formed on the thick-film insulating layer 21 through the inside conductive patterns 25 and the resistive element 12. Accordingly, the thick-film resistive element 12 is disposed within the multilayer wiring substrate 10 a. In this case, a plurality of via holes 26 are formed in the thick-film insulating layer 22 to expose the both end portions (corresponding to terminal portions) of the thick-film resistive element 12 therefrom.
    [0054] The terminal electrodes [0054] 12 a for the thick-film resistive element 12 are then formed in the via holes 26 and surface conductive patterns 27 are formed on the thick-film insulating layer 22 by printing and firing steps using conductive paste. Incidentally, it is desirable for each of the thick-film insulating layers 21, 22 to be formed by performing a formation step for more than two times. The other features and effects are the same as those in the first embodiment.
    [0055] (Fourth Embodiment) [0055]
    [0056] FIG. 7 shows a fourth preferred embodiment, and only points different from the first embodiment will be explained. In the fourth embodiment, a multilayer wiring substrate [0056] 28 is formed from well-known green sheets. Specifically, the multilayer wiring substrate 28 is composed of three insulating layers 29 a-29 c laminated with one another. A thick-film resistive element (passive circuit element) 30 and inside conductive patterns 31 are disposed on the insulating layer 29 a as the lowermost layer. The thick-film resistive element 30 in this embodiment is preferably formed from alumina powder and metallic material such as tungsten (W) or molybdenum (Mo).
    [0057] The insulating layer [0057] 29 c as an intermediate layer is formed to have a plurality of via holes 32 for exposing the both end portions (corresponding to terminal portions) of the thick-film resistive element 30 and specific portions of the inside conductive patterns 31. The via holes 32 are filled with terminal electrodes 30 a for the thick-film resistive element 30 and terminal electrodes 31 a for the inside conductive patterns 31. Inside conductive patterns 33 are further formed on the insulating layer 29 b. Some of the surface conductive patterns 33 are connected to the terminal electrodes 30 a, 31 a.
    [0058] The insulating layer [0058] 29 c as the uppermost layer is formed to have a plurality of via holes 34 for exposing specific portions of the inside conductive patterns 33, and conductive fills 34 a are formed to fill the via holes 34. Further, surface conductive patterns 35 are formed on the upper surface of the insulating layer 39 c. Some of the surface conductive patterns 35 are connected to the conductive fills 34 a.
    [0059] The multilayer wiring substrate [0059] 28 described above is manufactured by the following steps. That is, resistive paste for the thick-film resistive element 30 and conducive paste for the inside conductive patterns 31 are printed on a green sheet which is to be the insulating layer 29 a. The via holes 32, 34 are formed in respective green sheets for the insulating layers 29 b, 29 c by a punching step, and the terminal electrodes 31 a, the inside conductive patterns 33, the conducive fills 34 a, and the surface conductive patterns 35 are printed on and in the respective green sheets having the via holes 32. Thereafter, the tree green sheets are laminated with one another and are hot-pressed. In this state, after the laminated green sheets are cut into a shape corresponding to the multilayer wiring substrate 28, it is baked. If necessary, the surface conductive patterns 35 are plated with copper, nickel, gold or the like. As a result, the multilayer wiring substrate 28 is completed. The other features and effects are the same as those in the first embodiment.
    [0060] (Other Embodiments) [0060]
    [0061] As a modified example of the first embodiment, when a resistive pattern in which resistors R[0061] 1, R2 are electrically connected in series as shown in FIG. 8 is formed in the multilayer wiring substrate, the following structure can be adopted. That is, as shown in FIG. 9, a thick-film resistive element (passive circuit element) 36 formed between the insulating substrate 11 and the thick-film insulating layer 14 has a pair of terminal electrodes 36 a at the both end portions thereof and a terminal electrode 36 b at a position capable of dividing a value of resistance of the resistive element 36 into two values of resistance corresponding to the resistors R1, R2.
    [0062] Also, when a resistive pattern in which resistors R[0062] 3, R4, R5 are electrically connected as shown in FIG. 10 is formed, the structure of the first embodiment may be modified as shown in FIG. 11. That is, a pair of terminal electrodes 37 a are formed at the both end portions of a thick-film resistive element (passive circuit element) 37. Additionally, another via hole is formed in the insulating layer 14 to expose the thick-film resistive element 37 at a position capable of dividing the value of resistance of the resistive element 37 into two values of resistance corresponding to the resistors R3, R4, and the via hole is filled with a resistive member 37 b for the resistor R5.
    [0063] In the above two cases, the terminal electrodes [0063] 36 b and the resistive member 37 b are also formed by printing and firing pastes. The structures shown in FIGS. 9, 11 including the terminal electrode 36 b and the resistive element 37 b may be adopted to the other embodiments. For example, when the terminal electrode 36 b or the resistive element 37 b is applied to the fourth embodiment disclosing the green sheet lamination substrate, after the paste for the terminal electrode 36 b or the resistive element 37 b is embedded in the corresponding green sheet, all of the green sheets are laminated and are baked together.
    [0064] In the above-mentioned embodiments, although the thick-film resistive element is disposed within the multilayer wiring substrate as a passive circuit element, the passive circuit element is not limited to that and may be a inductor element or a capacitor element formed from a thick-film paste material. While the present invention has been shown and described with reference to the foregoing preferred embodiments, it will be apparent to those skilled in the art that changes in form and detail may be made therein without departing from the scope of the invention as defined in the appended claims. [0064]
    权利要求:
    Claims (18)
    [1" id="US-20010003053-A1-CLM-00001] 1. A multilayer substrate for a hybrid integrated circuit formed through a firing step, the multilayer substrate comprising:
    an insulating base substrate;
    a passive circuit element disposed above the base substrate;
    an insulating member disposed on the insulating base substrate with the passive circuit element interposed therebetween, the insulating member having a via hole for exposing a part of the passive circuit element; and
    a terminal electrode disposed in the via hole to directly contact the part of the passive circuit element.
    [2" id="US-20010003053-A1-CLM-00002] 2. The multilayer substrate of
    claim 1 , further comprising an insulating layer disposed between the insulating base substrate and the passive circuit element.
    [3" id="US-20010003053-A1-CLM-00003] 3. The multilayer substrate of
    claim 1 , wherein the passive circuit element is disposed directly on the insulating base substrate.
    [4" id="US-20010003053-A1-CLM-00004] 4. The multilayer substrate of
    claim 1 , wherein:
    the insulating member is a thin-film insulating layer formed on the insulating base substrate by firing; and
    the via hole is formed to pass through the insulating member.
    [5" id="US-20010003053-A1-CLM-00005] 5. The multilayer substrate of
    claim 1 , wherein:
    the insulating base substrate is composed of a plurality of green sheets laminated with one another;
    the insulating member is composed of a green sheet laminated with the insulating base substrate; and
    the via hole is formed to pass through the insulating member before the insulating member is laminated with the insulating base substrate.
    [6" id="US-20010003053-A1-CLM-00006] 6. The multilayer substrate of
    claim 1 , wherein:
    the via hole has first and second via holes;
    a terminal electrode is disposed in the first via hole; and
    a resistive member is disposed in the second via hole.
    [7" id="US-20010003053-A1-CLM-00007] 7. A method of manufacturing a multilayer substrate for a hybrid integrated circuit, the method comprising steps of:
    disposing a passive circuit element material at a specific portion on an insulating base substrate;
    firing the passive circuit element material to form a passive circuit element;
    disposing an insulating material to cover the passive circuit element and to have a via hole for exposing a part of the passive circuit element therefrom;
    firing the insulating material to form a thick-film insulating layer on the passive circuit element;
    filling the via hole with a conductive material so that the conductive material directly contact the passive circuit element; and
    firing the conductive material to form a terminal electrode contacting the passive circuit element in the via hole.
    [8" id="US-20010003053-A1-CLM-00008] 8. The method of
    claim 7 , wherein:
    the base substrate is composed of an insulating substrate and an insulating layer disposed on the insulating substrate; and
    the passive circuit element material is disposed on the insulating layer.
    [9" id="US-20010003053-A1-CLM-00009] 9. The method of
    claim 7 , wherein the passive circuit element is a resistive element, the method further comprising a step of trimming the resistive element while measuring a value of resistance of the resistive element, after the step of firing the passive element material.
    [10" id="US-20010003053-A1-CLM-00010] 10. The method of
    claim 9 , wherein the value of resistance of the resistive element is measured by a probe.
    [11" id="US-20010003053-A1-CLM-00011] 11. The method of
    claim 9 , wherein the value of resistance of the resistive element is measured through the terminal electrode.
    [12" id="US-20010003053-A1-CLM-00012] 12. The method of
    claim 9 , wherein:
    the steps of disposing and firing the insulating material are repeated more than one time; and
    the step of trimming the resistive element is carried out after the steps of disposing and firing the insulating material are carried out respectively one time.
    [13" id="US-20010003053-A1-CLM-00013] 13. The method of
    claim 9 , wherein:
    the steps of disposing and firing the insulating material and filling the via hole with the conductive material are repeated more than one time before the step of firing the conductive material; and
    the step of trimming the resistive element is carried out after the steps of disposing and firing the insulating material are carried out respectively one time.
    [14" id="US-20010003053-A1-CLM-00014] 14. The method of
    claim 13 , wherein:
    the step of trimming the resistive element is carried out after the steps of disposing and firing the insulating material and filling the via hole with the conductive material are carried out one time.
    [15" id="US-20010003053-A1-CLM-00015] 15. The method of
    claim 7 , wherein;
    the via hole has first and second via holes;
    the first via hole is filled with the conductive material; and
    the second via hole is filled with a resistive material to form a resistor in the second via hole.
    [16" id="US-20010003053-A1-CLM-00016] 16. A method of manufacturing a multilayer substrate for a hybrid integrated circuit, the method comprising steps of:
    printing a passive circuit element material on a first green sheet;
    forming a via hole through a second green sheet;
    filling the via hole with a conductive material;
    laminating the first and second green sheets so that the conductive material filling the via hole entirely contacts the passive circuit element material printed on the first green sheet; and
    firing the laminated first and second green sheets.
    [17" id="US-20010003053-A1-CLM-00017] 17. The method of
    claim 16 , wherein the passive circuit material and the conductive material are in a paste state.
    [18" id="US-20010003053-A1-CLM-00018] 18. The method of
    claim 16 , wherein;
    the via hole has first and second via holes;
    the first via hole is filled with the conductive material; and
    the second via hole is filled with a resistive material to form a resistor in the second via hole.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20050087841A1|2002-10-16|2005-04-28|Koki Ishizaki|Multilayer electronic substrate, and the method of manufacturing multilayer electronic substrate|
    US9012976B2|2012-07-27|2015-04-21|Kabushiki Kaisha Toshiba|Semiconductor device and method for manufacturing the same|
    US9136392B2|2012-08-28|2015-09-15|Kabushiki Kaisha Toshiba|Semiconductor memory device and method for manufacturing the same|
    CN109819582A|2017-11-22|2019-05-28|奇酷互联网络科技（深圳）有限公司|Circuit board, electric quantity monitoring circuit, circuit board manufacturing method and electronic equipment|US4285001A|1978-12-26|1981-08-18|Board Of Trustees Of Leland Stanford Jr. University|Monolithic distributed resistor-capacitor device and circuit utilizing polycrystalline semiconductor material|
    US4349862A|1980-08-11|1982-09-14|International Business Machines Corporation|Capacitive chip carrier and multilayer ceramic capacitors|
    JPS5771160A|1980-10-22|1982-05-01|Sony Corp|Manufacture of thick film printed circuit substrate|
    KR900004379B1|1983-09-16|1990-06-23|마쯔시다덴기산교 가부시기가이샤|Multilayer ceramic substrate and method of making the same|
    JP2712295B2|1988-05-26|1998-02-10|株式会社デンソー|Hybrid integrated circuit|
    JP2707717B2|1989-04-27|1998-02-04|富士通株式会社|Hybrid integrated circuit|
    US5254493A|1990-10-30|1993-10-19|Microelectronics And Computer Technology Corporation|Method of fabricating integrated resistors in high density substrates|
    EP0496491A1|1991-01-22|1992-07-29|National Semiconductor Corporation|Leadless chip resistor capacitor carrier for hybrid circuits and a method of making the same|
    JPH0677660A|1992-08-26|1994-03-18|Sumitomo Kinzoku Ceramics:Kk|Ceramic circuit board provided with resistor|
    DE4343934B4|1992-12-22|2005-08-25|Denso Corp., Kariya|Method for producing multiple thick-film substrates|
    JPH06232562A|1993-01-29|1994-08-19|Mitsubishi Electric Corp|Printed wiring board and manufacture thereof|
    US5514612A|1993-03-03|1996-05-07|California Micro Devices, Inc.|Method of making a semiconductor device with integrated RC network and schottky diode|
    US5633785A|1994-12-30|1997-05-27|University Of Southern California|Integrated circuit component package with integral passive component|
    JPH08335440A|1995-06-08|1996-12-17|Matsushita Electron Corp|Gas discharge type display device and its manufacture|
    US5891795A|1996-03-18|1999-04-06|Motorola, Inc.|High density interconnect substrate|
    US5847442A|1996-11-12|1998-12-08|Lucent Technologies Inc.|Structure for read-only-memory|US8421158B2|1998-12-21|2013-04-16|Megica Corporation|Chip structure with a passive device and method for forming the same|
    US20030112110A1|2001-09-19|2003-06-19|Mark Pavier|Embedded inductor for semiconductor device circuit|
    US7239524B2|2001-10-12|2007-07-03|Intel Corporation|Resistive element apparatus and method|
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    JP3896029B2|2002-04-24|2007-03-22|三洋電機株式会社|Method for manufacturing hybrid integrated circuit device|
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    DE102004038988B3|2004-08-10|2006-01-19|Siemens Ag|Gas mass flow measurement system for various applications has substrate with ceramic particles in organic matrix holding heating elements with temperature sensors|
    US7135377B1|2005-05-20|2006-11-14|Phoenix Precision Technology Corporation|Semiconductor package substrate with embedded resistors and method for fabricating same|
    US7768055B2|2005-11-30|2010-08-03|International Business Machines Corporation|Passive components in the back end of integrated circuits|
    KR100789521B1|2006-09-28|2007-12-28|삼성전기주식회사|Fabricating method of multi layer printed circuit board|
    JP2009135196A|2007-11-29|2009-06-18|Fujikura Ltd|Multilayer printed wiring board and method of manufacturing the same|
    JP2011228453A|2010-04-19|2011-11-10|Jtekt Corp|Multilayer circuit board, motor control device and vehicle steering device|
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    JP5644945B2|2011-06-29|2014-12-24|株式会社村田製作所|Multilayer ceramic substrate and manufacturing method thereof|
    KR20170053401A|2015-11-06|2017-05-16|삼성전자주식회사|Antenna and electronic device having it|
    DE102016106681A1|2016-04-12|2017-10-12|First Sensor Lewicki GmbH|Electronic module|
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    法律状态:
    2002-09-12| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2006-03-13| FPAY| Fee payment|Year of fee payment: 4 |
    2010-03-18| FPAY| Fee payment|Year of fee payment: 8 |
    2014-03-27| FPAY| Fee payment|Year of fee payment: 12 |
    优先权:
    申请号 | 申请日 | 专利标题
    JP22428197A|JP4032459B2|1997-08-05|1997-08-05|Hybrid integrated circuit substrate and method of manufacturing the same|
    JP9-224281||1997-08-05||
    US09/128,670|US6201286B1|1997-08-05|1998-08-04|Multilayer wiring substrate for hybrid integrated circuit and method for manufacturing the same|
    US09/772,873|US6458670B2|1997-08-05|2001-01-31|Method of manufacturing a circuit substrate|US09/772,873| US6458670B2|1997-08-05|2001-01-31|Method of manufacturing a circuit substrate|
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